Integrated circuits or semiconductor chips are typically encapsulated in a protective and insulating packaging material. The packaging material should provide a good balance between physical and chemical properties and costs. For typical semiconductor chips, the package is fabricated by a mould process involving hydraulic machines. The hydraulic machines are not compatible with front end cluster tools for gas phase deposition. The fabrication process of the package is not integrated into the fabrication process of the other functional layers of the semiconductor chip. Therefore, the mould process does not benefit from the cost down-scaling provided by front end processes.
For front end processes, the cost per semiconductor chip is approximately linear to the chip's surface area. The linear approximation of cost, however, is not applicable to the mould process. For instance, smaller chips in the same package require a higher quantity of encapsulation material or smaller chips per wafer require more packages and therefore more mould material and production capacity. The costs for the mould material and the mould process are typically high, especially for power semiconductors.
In addition, for very small semiconductor chips, the fluid mechanics of mould materials may not be compatible with the isolation, humidity resistance, or temperature resistance requirements of the semiconductor chips. In fact, voids may be created within the mould material and/or imperfections of the adhesion may result between the active layers of the semiconductor chips and the package layer of the semiconductor chips.
Further, the mould process throughput is relatively low. The fabrication process flow of the semiconductor chips is interrupted for the mould process and continued ex-situ. Because the fabrication process flow is interrupted and continued ex-situ, the contamination risk to the semiconductor chips is high. The contamination risk increases as the semiconductor chips get smaller.
In addition, the mould process results in thermal-mechanical stresses on the semiconductor chips. The mould process typically has a mould temperature of about 175° C. Due to the moulding temperature, there is significant thermal-mechanical stress on the semiconductor chips at room temperature, and the thermal-mechanical stress on the semiconductor chips increases as the temperature of the semiconductor chips decreases.
For these and other reasons, there is a need for the present invention.